The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
Integrated circuit devices comprise a multitude of material layers, each material layer meeting another material layer at an interface. The interface may be subjected to various processing and manufacturing steps and preferably maintains interface integrity throughout manufacture of the integrated circuit device. For example, it is desired that each interface maintain peeling integrity (i.e., the two layers do not peel away from one another, which can sometimes form a void). It has been observed that conventional interfaces, particularly copper-copper interfaces (such as an interface between two copper layers) exhibit peeling, which degrades overall integrated circuit device performance. A need therefore exists to provide an interface structure for addressing interface peeling issues.